I can't do much about the start of a TS packet not appearing at the start of a frame - that's how it comes from the tuner/demodulator into the bt878 then over to the host pc.
Unless the whole capture has rubbish data, any TS parser should ignore any partial packet and sync up with the first 0x47 header.
I don't know what's causing the rest of the screwups through the remainder of the capture, but I have my suspicions.
Imagine a RISC programme laid out in memory where we capture 3 frames "a", "b" and "c". The programme makes the bt878 hardware copy TS data to host memory. We start with frame "a", then "b" then "c" and then jump back to "a" and so on. Windows O/S components, through AVStreaming give me chunks of physical memory. I programme the RISC instructions to copy data from the card into the physical host memory. Because the memory chunks given to me don't line up exactly with what the bt878 can handle I have to break it up further - the chunks themselves can vary in their layout.
For example, frame "a" might consist of 3 instructions, frame "b" four instructions etc. See the 1st column:
CODE
1st 2nd 3rd
1 a a a
2 a a a
3 a a a
4 b a a
5 b b b
6 b b b
7 b b b
8 c c x
9 c c x
10 c c x
11 c c x
12 j j x
1 a a a
2 a a a
3 a a a
4 b a a
5 b b b
6 b b b
7 b b b
8 c c x
9 c c x
10 c c x
11 c c x
12 j j x
After the card has transferred frame "a" to host memory, I release the memory back to AVStream, the memory is used by a downstream filter and once it's finished with it, it goes back into the pool for AVStream to reissue to me for reuse.
What can also happen though, is I might release frames "a" and "b" and AVStream will reissue the "b" frame's memory to me before the "a" frame's memory (see the 2nd column). You can see the new "a" frame now has 4 instructions instead of 3 (potentially overwriting the data at line 4). This is OK as the new "b" frame has already been given back to us (it's the old "a") so we know it's not in use.
If however I had released frames "c" and "a" and AVStream reissued their memory in reverse order, we might get the 3rd column. From the 1st column frame "b" is just in the process of having it's RISC code run in the bt878 at line 4, but you can see in the 3rd column I've overwritten the first "b" instruction with the final new "a" instruction. Depending on timing, things will get out of whack.
I'm sorry if this isn't all that clear, but I have a potential solution.
CODE
1st 2nd
1 a a
2 a a
3 a a
4 b b
5 b b
6 b b
7 b b
8 c c
9 c c
10 c c
11 c c
12 j a
13 a
14 a
15 a
16 b
17 b
18 b
19 b
20 c
21 c
22 c
23 j
1 a a
2 a a
3 a a
4 b b
5 b b
6 b b
7 b b
8 c c
9 c c
10 c c
11 c c
12 j a
13 a
14 a
15 a
16 b
17 b
18 b
19 b
20 c
21 c
22 c
23 j
By using double the buffer for the RISC programme I remove the risk (pun intended) of overwriting RISC code that might be about to execute. When I programme frame "a" from line 12 there's no risk of overwriting frame "b" from line 4.
Spectrum